Semiconductor integrated circuit device

ABSTRACT

Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an analog semiconductor integratedcircuit device which is required to have a high output voltage accuracy.

2. Description of the Related Art

In a semiconductor integrated circuit, a constant voltage circuit whichoutputs a constant voltage irrespective of the power supply voltage canbe realized in a simplified manner at a low cost by, as illustrated inFIGS. 2A and 2B, connecting in series an enhancement type N-channel MOSfield effect transistor (hereinafter referred to as NMOS) and adepression type N-channel MOS field effect transistor. Thus, theconstant voltage circuit of this type is widely adopted.

In FIG. 2A, in an enhancement type NMOS 101, a source terminal and abody terminal which is connected to a P-type well region (hereinafterreferred to as P-well) are connected to a ground terminal at the lowestpotential in the constant voltage circuit, while a gate terminal and adrain terminal are connected to a source terminal of a depression typeNMOS 102.

Further, in the depression type NMOS 102, a drain terminal is connectedto a power supply voltage terminal at the highest potential in theconstant voltage circuit, while a gate terminal is connected to thesource terminal of the NMOS 102.

When such connection is made, first, the NMOS 101 operates in saturationbecause the potential of the gate terminal and the potential of thedrain terminal are the same. With regard to the NMOS 102, when a voltageof a certain level or higher is applied to the drain terminal, the NMOS102 operates in saturation. Because currents which pass through therespective NMOSs are the same, the following simple relationalexpression which expresses a state in which the saturation currents arebalanced with each other is obtained:

Kne(Vg1−-Vtne)² =Knd(Vg2−Vtnd)²   (a)

where Kne, Vg1, and Vtne are the transconductance, the gate potential,and the threshold voltage of the NMOS 101, respectively, and Knd, Vg2,and Vtnd are the transconductance, the gate potential, and the thresholdvoltage of the NMOS 102, respectively.

From the above relational expression, an output value Vout of theconstant voltage circuit is as follows:

Vout=(Knd/Kne)^(1/2) ·∥Vtnd∥+Vtne   (b)

As expressed above, Vout can be adjusted by the element characteristicsof the respective NMOSs. In the case illustrated in FIGS. 2A and 2B,however, Vtnd and Knd are the threshold voltage and the transconductancedetermined under the back bias effect caused by the voltage Vout sincethe potential of the body terminal of the NMOS 102 is lower than thepotential of the source terminal. To prevent the change incharacteristics due to the back bias effect the body terminal will beconnected to the source terminal. In this case, in order that thepotentials of the respective P-well regions on which the NMOSs 101 and102 are formed can be changed, it is necessary to select an N-typesubstrate as the semiconductor substrate to form the P-well regions eachisolated by PN junction, and form the NMOSs 101 and 102 on the P-wellregions, respectively. Except such case as mentioned above the circuitstructure illustrated in FIGS. 2A and 2B is irrelevant to the polarityof the semiconductor substrate and is highly versatile.

Next, a method of manufacturing the above-mentioned conventionalsemiconductor integrated circuit device is schematically described withreference to FIG. 4. In the description, the same terminology is used asin FIGS. 2A and 2B.

First, a P-type semiconductor substrate or an N-type semiconductorsubstrate is prepared. After P-type impurities of boron (B) or BF₂ areinjected by ion implantation into desired regions in which the NMOSs areto be formed, thermal diffusion is performed to form the P-well regions(Step a). The amount of the injected impurities and the conditions ofthe thermal diffusion are selected so that the impurity concentration inthe P-well regions lies between 1×10¹⁶ cm⁻³ and 1×10¹⁷ cm⁻³ and thedepth of the P-well regions is several micrometers.

Next, in order to electrically isolate the elements from each other,LOCOS or the like is used to form an element isolation region (Step b).

Next, in order to adjust the threshold voltage of the enhancement typeNMOS to be a desired value, P-type impurities of boron (B) or BF₂ areinjected by ion implantation into the region in which the enhancementtype NMOS is to be formed (Step c).

Next, in order to adjust the threshold voltage of the depression typeNMOS to be a desired value, N-type impurities of phosphorus (P) orarsenic (As) are injected by ion implantation into the region in whichthe depression type NMOS is to be formed (Step d).

Next, a gate oxide film of the enhancement type NMOS and the depressiontype NMOS is formed by thermal oxidation (Step e).

Next, in order to form gate electrodes of the enhancement type NMOS andthe depression type NMOS, a poly-Si film is deposited and impurities ata high concentration are injected so as to attain 1×10¹⁹ cm⁻³ or higherby ion implantation or thermal diffusion, and patterning is carried out(Step f).

Next, in order to form source/drain regions and regions for givingpotentials of P-well regions (referred to as body regions) underchannels of the enhancement type NMOS and the depression type NMOS,impurities are injected by ion implantation. In this case, N-type highconcentration impurities for forming the source/drain have aconcentration 1×10¹⁹ cm⁻³ or higher and are arranged at a predetermineddistance from the end of the gate electrode. On the other hand, N-typelow concentration impurity regions of 5×10¹⁶ cm⁻³ to 5×10¹⁷ cm⁻³ areformed from the N-type high concentration impurity regions to the endsof the gate electrode, respectively. The N-type low concentrationimpurity regions operate to alleviate the electric field when a highvoltage is applied (Step g).

Next, an insulating film which is an oxide film is deposited on theentire surface. After contact holes are formed at predeterminedlocations, in order to give potentials of the gates, sources, drains,and bodies of the respective NMOS elements, metal wiring is formed bysputtering and patterning a metal film (Step h).

Another exemplary conventional constant voltage circuit is describedwith reference to FIGS. 3A and 3B. In FIGS. 3A and 3B, the same NMOSelement as illustrated in FIGS. 2A and 2B is used, and only the wiringmethod is changed. Specifically, a change is made so that the gateterminal of the depression type NMOS 102 is connected to the groundterminal which is the lowest potential in the constant voltage circuit.Because the gate voltage of the depression type NMOS 102 is shifted to anegative side by Vout, the output voltage and the current consumptioncan be remarkably reduced. The system of the above-mentioned constantvoltage circuit is disclosed in, for example, Japanese PatentApplication Laid-open No. 2008-293409.

When a conventional packaging is performed for encapsulating theabove-mentioned semiconductor integrated circuit device including a lowvoltage circuit in a resin package, the following problem arises.

For example, when the threshold voltages and the transconductances ofthe enhancement type NMOS and the depression type NMOS vary in massproduction, the output voltage of the constant voltage circuit varies.Further, the output voltage also fluctuates when the environment such asthe temperature fluctuates. Accordingly, a method of realizing an NMOSelement structure or a semiconductor integrated circuit system which canreduce fluctuations in output voltage of a constant voltage circuit isdesired.

SUMMARY OF THE INVENTION

In order to solve such a problem, according to one embodiment of thepresent invention, a semiconductor integrated circuit device includes anenhancement type first N-channel type MOS transistor and a depressiontype second N-channel type MOS transistor, the first NMOS being formedon a P-type well region, having a gate oxide film, a gate electrode, andsource and drain regions each of which includes an N-type lowconcentration region and an N-type high concentration region, and havinga positive threshold voltage, the second NMOS being formed on a P-typewell region, having a gate oxide film, a gate electrode, source anddrain regions each of which includes an N-type low concentration regionand an N-type high concentration region, and an N-type channel impurityregion, and having a negative threshold voltage. A gate terminalconnected to the gate electrode and a drain terminal connected to thedrain region of the first NMOS are connected to a source terminalconnected to the source region and a gate terminal of the second NMOS. Asource terminal and a body terminal connected to the P-type well regionof the first NMOS are connected to a ground potential which is thelowest potential in a circuit, a drain terminal of the second NMOS isconnected to a power supply voltage which is the highest potential inthe circuit, and a body terminal of the second NMOS is connected to theground potential. The impurity concentration of the P-type well regionon which the second NMOS is arranged is higher than the impurityconcentration of the P-type well region on which the first NMOS isarranged.

According to another embodiment of the present invention, asemiconductor integrated circuit device includes an enhancement typefirst N-channel type MOS transistor and a depression type secondN-channel type MOS transistor, the first NMOS being formed on a P-typewell region, having a gate oxide film, a gate electrode, and source anddrain regions each of which includes an N-type low concentration regionand an N-type high concentration region, and having a positive thresholdvoltage, the second NMOS being formed on a P-type well region, having agate oxide film, a gate electrode, source and drain regions each ofwhich includes an N-type low concentration region and an N-type highconcentration region, and an N-type channel impurity region, and havinga negative threshold voltage. A gate terminal connected to the gateelectrode and a drain terminal connected to the drain region of thefirst NMOS are connected to a source terminal connected to the sourceregion of the second NMOS. A source terminal and a body terminalconnected to the P-type well region of the first NMOS are connected to aground potential which is the lowest potential in a circuit, a drainterminal of the second NMOS is connected to a power supply voltage whichis the highest potential in the circuit, and a gate terminal and a bodyterminal of the second NMOS are connected to the ground potential. Theimpurity concentration of the P-type well region on which the secondNMOS is arranged is higher than the impurity concentration of the P-typewell region on which the first NMOS is arranged.

In the semiconductor integrated circuit device, the impurityconcentration of the P-type well region on which the first NMOS isarranged is lower than 1×10¹⁷/cm³ and the impurity concentration of theP-type well region on which the second NMOS is arranged is higher than1×10¹⁷/cm³.

Alternatively, in the semiconductor integrated circuit device, theP-type well regions of the first and second NMOSs have the same impurityconcentration, but a P-type impurity layer having a partly higherimpurity concentration than that of the P-type well region is providedunder the N-type channel impurity region of the second NMOS.

Further, in the semiconductor integrated circuit device, the impurityconcentration of the P-type well region on which the first NMOS isarranged is lower than 1×10¹⁷/cm³ and the impurity concentration of theP-type impurity layer having a partly higher impurity concentration thanthat of the P-type well region under the N-type channel impurity regionof the second NMOS is higher than 1×10¹⁷/cm³.

Alternatively, in the semiconductor integrated circuit device, each ofthe source/drain regions of the second NMOS includes an N-type lowconcentration region in proximity to the gate electrode and an N-typehigh concentration region which is formed under a contact hole and incontact with the N-type low concentration region, and the length of theN-type low concentration region in the source region from an end of thegate electrode to the N-type high concentration region is larger thanthe length of the N-type low concentration region in the drain regionfrom another end of the gate electrode to the N-type high concentrationregion.

According to the present invention, a highly accurate analogsemiconductor integrated circuit device can be provided which caninhibit fluctuations in output voltage of a constant voltage circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a schematic sectional view of a semiconductor integratedcircuit device according to a first embodiment of the present invention;

FIG. 2A is a schematic sectional view of a conventional semiconductorintegrated circuit device;

FIG. 2B is a circuit connection diagram of the conventionalsemiconductor integrated circuit device;

FIG. 3A is a schematic sectional view of another conventionalsemiconductor integrated circuit device;

FIG. 3B is a circuit connection diagram of the conventionalsemiconductor integrated circuit device;

FIG. 4 is a process flow chart for manufacturing the conventionalsemiconductor integrated circuit device;

FIG. 5 is a process flow chart for manufacturing the semiconductorintegrated circuit device according to the first embodiment of thepresent invention;

FIG. 6 is a graph showing the relationship between a gate voltage and adrain current in a depression type NMOS transistor;

FIG. 7 is a schematic sectional view of another semiconductor integratedcircuit device according to the first embodiment of the presentinvention;

FIG. 8 is a schematic sectional view of a semiconductor integratedcircuit device according to a second embodiment of the presentinvention;

FIG. 9 is a schematic sectional view of another semiconductor integratedcircuit device according to the second embodiment of the presentinvention;

FIG. 10 is a process flow chart for manufacturing the semiconductorintegrated circuit device according to the second embodiment of thepresent invention;

FIG. 11 is a schematic sectional view of a semiconductor integratedcircuit device according to a third embodiment of the present invention;and

FIG. 12 is a schematic sectional view of another semiconductorintegrated circuit device according to the third embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention are described in the following withreference to the attached drawings. FIG. 1 is a sectional view of asemiconductor integrated circuit device according to a first embodimentof the present invention, and is an example in which a constant voltagecircuit effectively uses a back bias applied to a depression type NMOS.

FIG. 1 is a sectional view in which the conventional constant voltagecircuit illustrated in FIGS. 2A and 2B has a feature of the presentinvention added thereto. The difference is that a P-well region on whichan enhancement type NMOS 101 is arranged and a P-well region on which adepression type NMOS 102 is arranged are individually formed, and theimpurity concentrations of the P-well regions are different from eachother. Specifically, the impurity concentration of a P-well region 5 onwhich the enhancement type NMOS 101 is arranged is 1×10¹⁵/cm³ or higherand lower than 1×10¹⁷/cm³, which is an ordinary concentration, while theimpurity concentration of a P-well region 6 on which the depression typeNMOS 102 is arranged is a special concentration of 1×10¹⁷/cm³ or higher.

In this manner, an effect of enhancing the back bias effect inherentlyapplied to a body terminal of the depression type NMOS is exerted.

When a negative back bias is applied to a body terminal of an NMOS,depending on the impurity profile in a channel, the threshold voltagegenerally shifts to a higher side and the transconductance(corresponding to the slope of the voltage-current characteristics shownin FIG. 6) generally shifts to a lower side.

This effect becomes more remarkable as the impurity concentration of theP-well region becomes higher. The reason is as follows. The thresholdvoltage becomes higher by an amount corresponding to the gate voltagenecessary for keeping the balance with charge in a depletion layer underthe gate which is caused when the back bias is applied. Because anincrease in the impurity concentration of the P-well region increasesthe charge density in the depletion layer, the threshold voltage becomesfurther higher. Further, in that case, because the electric fieldbecomes stronger in a direction perpendicular to a current in a planedirection through the channel, the carrier mobility is lowered to lowerthe transconductance.

Such an effect is considered with regard to the semiconductor integratedcircuit device illustrated in FIG. 1. For example, in Eq. (b), when Vtnechanges for some reason, in a conventional case, the output voltagechanges in accordance with the change in Vtne. However, due to the backbias effect, the following feedback remarkably acts so as to inhibit thechange in Vout to inhibit the fluctuations. In this embodiment, becausethe impurity concentration of the P-well region on which the depressiontype NMOS is arranged is higher, the following effect becomes moreremarkable. A similar effect acts with regard to change in Kne, Vtnd,and Knd.

-   -   increase (decrease) in Vtne    -   →increase (decrease) in Vout    -   →increase (decrease) in Vtnd/decrease (increase) in Knd due to        the back bias effect    -   →decrease (increase) in Vout

Further, a similar effect can be obtained when these elementcharacteristics are changed by external factors such as temperature, andthe output voltage of the constant voltage circuit can be very stable.

Next, a method of manufacturing the semiconductor integrated circuitdevice of this embodiment is schematically described with reference toFIG. 5. In the description, like reference numerals are used todesignate like members in FIG. 1.

First, a P-type semiconductor substrate or an N-type semiconductorsubstrate 1 is prepared. After P-type impurities of boron (B) or BF₂ areinjected by ion implantation into desired regions in which the NMOSs areto be formed, thermal diffusion is performed to form the P-well regions(5 and 6) having different impurity concentrations from each other(Steps a and b). The amounts of the injected impurities and theconditions of the thermal diffusion are selected so that the impurityconcentration in the P-well region 5 is 1×10¹⁶ cm⁻³ or higher and lowerthan 1×10¹⁷ cm⁻³, the impurity concentration in the P-well region 6 is1×10¹⁷ cm⁻³ or higher, and the depths of the P-well regions 5 and 6 areseveral micrometers.

Next, in order to electrically isolate the elements from each other,LOCOS or the like is used to form an element isolation region (Step c).

Next, in order to adjust the threshold voltage of the enhancement typeNMOS to be a desired value, P-type impurities of boron (B) or BF₂ areinjected by ion implantation into the region in which the enhancementtype NMOS is to be formed (Step d).

Next, in order to adjust the threshold voltage of the depression typeNMOS to be a desired value, N-type impurities of phosphorus (P) orarsenic (As) are injected by ion implantation into the region in whichthe depression type NMOS is to be formed to form an N-type channelimpurity region 10 (Step e).

Next, a gate oxide film 9 of the enhancement type NMOS and thedepression type NMOS is formed by thermal oxidation (Step f).

Next, in order to form gate electrodes 8 of the enhancement type NMOSand the depression type NMOS, a poly-Si film is deposited and impuritiesat a high concentration are injected so as to attain 1×10¹⁹ cm⁻³ orhigher by ion implantation or thermal diffusion, and patterning iscarried out (Step g).

Next, in order to form source/drain regions 7 and regions for givingpotentials of P-well regions (referred to as body regions) underchannels of the enhancement type NMOS and the depression type NMOS,impurities are injected by ion implantation. In this case, N-type highconcentration impurities for forming the source/drain are injected at aconcentration so as to attain 1×10¹⁹ cm⁻³ or higher at a predetermineddistance from ends of the gate electrode. On the other hand, N-type lowconcentration impurity regions of 5×10¹⁶ cm³ to 5×10 ¹⁷ cm⁻³ are formedfrom the high concentration source impurity regions to the ends of thegate electrode, respectively. The N-type low concentration impurityregions function to alleviate the electric field when a high voltage isapplied (Step h).

Next, an insulating film which is an oxide film is deposited on theentire surface. After contact holes are formed at predeterminedlocations, in order to give potentials of the gates, sources, drains,and bodies of the respective NMOS elements, metal wiring (2 to 4) isformed by sputtering and patterning a metal film (Step i).

In FIG. 7, the gate terminal of the depression type NMOS 102 in FIG. 1is connected to a VSS terminal 104, and the semiconductor integratedcircuit device in FIG. 7 corresponds to the conventional semiconductorintegrated circuit device illustrated in FIGS. 3A and 3B. In FIG. 7,because the gate potential of the depression type NMOS is linked withincrease or decrease in output voltage, feedback acts so as to inhibitfluctuations in output voltage. In addition, the feedback due to theback bias effect described above with reference to FIG. 1 acts. In thisway, a more stable output potential can be realized.

FIG. 8 illustrates a second embodiment for realizing the back biaseffect as described with reference to FIG. 1. In FIG. 8, as in aconventional case, the enhancement type NMOS 101 and the depression typeNMOS 102 have the same P-well region 5, but a P-type channel impurityregion 11 having the impurity concentration higher than that of theP-well region is locally formed immediately below the N-type channelimpurity region 10 of the depression type NMOS 102. Such a structureenables the depression type NMOS 102 to obtain a sufficient back biaseffect similarly to the case illustrated in FIG. 1, and the stability ofthe output voltage of the constant voltage circuit can be improved.

In FIG. 9, the gate terminal of the depression type NMOS 102 illustratedin FIG. 8 is connected to a VSS terminal 103. In addition to thefeedback due to the gate potential of the depression type NMOS, thefeedback due to the back bias effect according to the present inventionacts, and a more stable output potential can be realized.

FIG. 10 schematically illustrates semiconductor manufacturing steps ofthe second embodiment. In this embodiment, after the step of injectingN-type impurities for the depression type NMOS 102 for adjusting thethreshold voltage illustrated in FIG. 4 in the conventional case, a step(e) of injecting P-type impurities such as boron (B) or BF₂ for thedepression type NMOS is added. In this case, the P-type impurity regionis formed by ion implantation, and the energy for the step is selectedso that, in terms of injection depth, the impurity concentration becomesthe highest immediately below the N-type channel impurity region.

By carrying out this step as the same mask step as the step of injectingthe N-type impurities prior to the step, the number of the mask steps isprevented from being increased. Because it is not necessary to prepare amask for forming the P-well region dedicated to the depression type NMOSas in the first embodiment, there is an advantage over the case of thefirst embodiment in that the manufacturing steps can be reduced torealize cost reduction.

FIG. 11 illustrates a third embodiment of the present invention in whichthe back bias effect as described with reference to FIG. 1 is obtainedby another method. In FIG. 11, with regard to the N-type lowconcentration source/drain regions 7 of the depression type NMOS 102,the source side extends longer than the drain side.

Generally, it is preferred that the low concentration source/drainregions be short insofar as no degradation in characteristics is caused.The reason is to reduce the footprint to contribute to cost reduction.However, according to the present invention, from the viewpoint ofenhancing the back bias effect, only the length of the N-type lowconcentration region on the source side of the depression type NMOS 102is extended to be at the level of several micrometers to several tens ofmicrometers, while the other N-type low concentration region is at theordinary level of several micrometers and is caused to be as small aspossible. Because this N-type low concentration region has a surfaceresistivity of several kilo-ohms per square to several tens of kilo-ohmsper square, when the depression type NMOS is operated, a drive currentof the transistor also passes through this N-type low concentrationregion, and voltage drop of several hundreds of millivolts to severalvolts is caused. This voltage drop causes voltage difference between thesource terminal and the body terminal in the channel region of thedepression type NMOS for the voltage drop, which is the back bias in thedepression type NMOS.

It can be said that this embodiment is a highly versatile method whichcan be applied to various kinds of semiconductor processes, because,although the necessary area increases, no special semiconductormanufacturing step is added.

In FIG. 12, the gate terminal of the depression type NMOS 102illustrated in FIG. 11 is connected to the VSS terminal 103. In additionto the feedback due to the gate potential of the depression type NMOS,the feedback due to the back bias effect according to the presentinvention acts, and a more stable output potential can be realized.

It goes without saying that the first to third embodiments describedabove are not independent of one another and an appropriate combinationthereof can enhance the effect. Although not illustrated, for example,in the depression type NMOS, the impurity concentration of the P-wellregion can be set to be higher and a P-type high concentration impurityregion can be formed under the N-type channel impurity region at thesame time. Further, by setting the impurity concentration of the P-wellregion to be higher and providing the P-type channel impurity region,and in addition, extending the N-type low concentration region on thesource side at the same time, the back bias effect can be enhanced tofurther improve the stability of the output voltage of the constantvoltage circuit.

What is claimed is:
 1. A semiconductor integrated circuit device,comprising: an enhancement type first N-channel type MOS transistorcomprising: a first gate oxide film formed on a first P-type wellregion; a first gate electrode; a first gate terminal connected to thefirst gate electrode; a first source region and a first drain region,each of which comprises an N-type low concentration region and an N-typehigh concentration region; a first drain terminal connected to the firstdrain region; a first source terminal connected to the first sourceregion; and a first body terminal connected to the first P-type wellregion, the first N-channel type MOS transistor having a positivethreshold voltage; and a depression type second N-channel type MOStransistor comprising: a second gate oxide film formed on a secondP-type well region; a second gate electrode; a second gate terminalconnected to the second gate electrode; a second source region and asecond drain region, each of which comprises an N-type low concentrationregion and an N-type high concentration region; a second drain terminalconnected to the second drain region; a second source terminal connectedto the second source region; a second body terminal connected to thesecond P-type well region; and an N-type channel impurity region, thesecond N-channel type MOS transistor having a negative thresholdvoltage, the first gate terminal and the first drain terminal beingconnected to the second source terminal and the second gate terminal,the first source terminal and the first body terminal being connected toa ground potential which is a lowest potential in a circuit, the seconddrain terminal being connected to a power supply voltage which is ahighest potential in the circuit, the second body terminal beingconnected to the ground potential, the second P-type well region havingan impurity concentration higher than an impurity concentration of thefirst P-type well region.
 2. A semiconductor integrated circuit device,comprising: an enhancement type first N-channel type MOS transistorcomprising: a first gate oxide film formed on a first P-type wellregion; a first gate electrode; a first gate terminal connected to thefirst gate electrode; a first source region and a first drain region,each of which comprises an N-type low concentration region and an N-typehigh concentration region; a first drain terminal connected to the firstdrain region; a first source terminal connected to the first sourceregion; and a first body terminal connected to the first P-type wellregion, the first N-channel type MOS transistor having a positivethreshold voltage; and a depression type second N-channel type MOStransistor comprising: a second gate oxide film formed on a secondP-type well region; a second gate electrode; a second gate terminalconnected to the second gate electrode; a second source region and asecond drain region, each of which comprises an N-type low concentrationregion and an N-type high concentration region; a second drain terminalconnected to the second drain region; a second source terminal connectedto the second source region; a second body terminal connected to thesecond P-type well region; and an N-type channel impurity region, thesecond N-channel type MOS transistor having a negative thresholdvoltage, the first gate terminal and the first drain terminal beingconnected to the second source terminal, the first source terminal andthe second body terminal being connected to a ground potential which isa lowest potential in a circuit, the second drain terminal beingconnected to a power supply voltage which is a highest potential in thecircuit, the second gate terminal and the second body terminal beingconnected to the ground potential, the second P-type well region havingan impurity concentration higher than an impurity concentration of thefirst P-type well region.
 3. A semiconductor integrated circuit deviceaccording to claim 1, wherein: each of the second source region and thesecond drain region comprises an N-type low concentration region inproximity to the second gate electrode and an N-type high concentrationregion provided in contact with the N-type low concentration region; anda length of the N-type low concentration region in the second sourceregion from an end of the second gate electrode to the N-type highconcentration region is larger than a length of the N-type lowconcentration region in the second drain region from another end of thesecond gate electrode to the N-type high concentration region.
 4. Asemiconductor integrated circuit device according to claim 2, wherein:each of the second source region and the second drain region comprisesan N-type low concentration region in proximity to the second gateelectrode and an N-type high concentration region provided in contactwith the N-type low concentration region; and a length of the N-type lowconcentration region in the second source region from an end of thesecond gate electrode to the N-type high concentration region is largerthan a length of the N-type low concentration region in the second drainregion from another end of the second gate electrode to the N-type highconcentration region.
 5. A semiconductor integrated circuit device,comprising: an enhancement type first N-channel type MOS transistorcomprising: a first gate oxide film formed on a first P-type wellregion; a first gate electrode; a first gate terminal connected to thefirst gate electrode; a first source region and a first drain region,each of which comprises an N-type low concentration region and an N-typehigh concentration region; a first drain terminal connected to the firstdrain region; a first source terminal connected to the first sourceregion; and a first body terminal connected to the first P-type wellregion, the first N-channel type MOS transistor having a positivethreshold voltage; and a depression type second N-channel type MOStransistor comprising: a second gate oxide film formed on a secondP-type well region; a second gate electrode; a second gate terminalconnected to the second gate electrode; a second source region and asecond drain region, each of which comprises an N-type low concentrationregion and an N-type high concentration region; a second drain terminalconnected to the second drain region; a second source terminal connectedto the second source region; a second body terminal connected to thesecond P-type well region; and an N-type channel impurity region, thesecond N-channel type MOS transistor having a negative thresholdvoltage, the first gate terminal and the first drain terminal beingconnected to the second source terminal and the second gate terminal,the first source terminal and the first body terminal being connected toa ground potential which is a lowest potential in a circuit, the seconddrain terminal being connected to a power supply voltage which is ahighest potential in the circuit, the second body terminal beingconnected to the ground potential, the first P-type well region and thesecond P-type well region having the same impurity concentration, thesemiconductor integrated circuit device further comprising a P-typeimpurity layer provided under the N-type channel impurity region, theP-type impurity layer having a partly higher impurity concentration thanthe impurity concentrations of the first P-type well region and thesecond P-type well region.
 6. A semiconductor integrated circuit device,comprising: an enhancement type first N-channel type MOS transistorcomprising: a first gate oxide film formed on a first P-type wellregion; a first gate electrode; a first gate terminal connected to thefirst gate electrode; a first source region and a first drain region,each of which comprises an N-type low concentration region and an N-typehigh concentration region; a first drain terminal connected to the firstdrain region; a first source terminal connected to the first sourceregion; and a first body terminal connected to the first P-type wellregion, the first N-channel type MOS transistor having a positivethreshold voltage; and a depression type second N-channel type MOStransistor comprising: a second gate oxide film formed on a secondP-type well region; a second gate electrode; a second gate terminalconnected to the second gate electrode; a second source region and asecond drain region, each of which comprises an N-type low concentrationregion and an N-type high concentration region; a second drain terminalconnected to the second drain region; a second source terminal connectedto the second source region; a second body terminal connected to thesecond P-type well region; and an N-type channel impurity region, thesecond N-channel type MOS transistor having a negative thresholdvoltage, the first gate terminal and the first drain terminal beingconnected to the second source terminal, the first source terminal andthe second body terminal being connected to a ground potential which isa lowest potential in a circuit, the second drain terminal beingconnected to a power supply voltage which is a highest potential in thecircuit, the second gate terminal and the second body terminal beingconnected to the ground potential, the first P-type well region and thesecond P-type well region having the same impurity concentration, andthe semiconductor integrated circuit device further comprising a P-typeimpurity layer provided under the N-type channel impurity region, theP-type impurity layer having a partly higher impurity concentration thanthe impurity concentrations of the first P-type well region and thesecond P-type well region.